1. Field of the Invention
The present invention relates to a method of using an e-fuse device, and more particularly to a method of fusing an e-fuse device by employing a multi-level voltage pulse.
2. Description of the Prior Art
As the integration of a semiconductor increases, the corresponding yield of the device may decrease. Because of the increasing density of memory cells within a semiconductor memory, memory fabrication techniques become more difficult and complicated. Since it is impossible to eliminate the presence of particles or other factors that causes defects, which decreases the yield, during the fabrication of a semiconductor device, a so-called redundancy circuit is conventionally used to make up the desired yield of a semiconductor device.
A redundant memory cell array is provided in the so-called redundancy circuit besides the regular memory array used to store binary data, wherein the redundant memory array replaces the defective memory cells within the regular memory array. Each of the memory cells within the redundant memory cell array is individually connected to the corresponding wordline and bitline. If a number of the memory cells found to be defective within the regular memory array is somewhere in the order of thousands after the test, the memory cells within the redundant memory cell array replace those memory cells found to be defective to make the memory still an irreproachable one.
Generally, the regular memory cell array and the redundant memory cell array in a conventional memory are connected through semiconductor fuse devices, which can be broken by a laser beam or an electrical current. In the case that a defective memory cell is found and needs to be recovered, the corresponding semiconductor fuse device is broken by a laser beam or an electrical current; if there are no defective memory cells found, semiconductor fuse devices remain intact. The kind of fuse device that is broken by an electric current when a defective memory cell is found is also known as an “e-fuse” device, which typically includes a strip of poly fuse with one end serially connected to a source/drain of a MOS transistor, and the other end of the poly fuse connected to a positive voltage. The MOS transistor has the other source/drain that is connected to ground, and a gate that is biased to a gate voltage to allow an electric current to flow through the poly fuse and break the poly fuse in a very short time.
Referring to FIG. 1, a Vg-Time plot showing a pulse voltage waveform applied to a gate of a MOS transistor of an e-fuse device to be broken according to prior art method is demonstrated. As shown in FIG. 1, the pulse voltage waveform is a single-level square waveform that can be generated by conventional voltage pulse generator. The simple pulse voltage waveform in FIG. 1 has a maximum voltage value VIH during time period T2-T1, and a minimum voltage value VIL that is typically 0 volt. Ordinarily, the maximum voltage value VIH is about the threshold voltage of the MOS transistor of the e-fuse device to be broken. Originally, the poly fuse strip of the e-fuse device has a resistance of about 100 ohm. After going through the fusing process, the resistance of the poly fuse strip ramps up to at least one mega ohm.
However, the prior art method of breaking the aforesaid e-fuse device is very difficult to control, thus leading to a low repair yield. According to the prior art, the process window for the maximum voltage value VIH is too small (±5%). Once the real maximum input voltage of the pulse exceeds the limit value, the poly-fuse strip ruptures immediately. Accordingly, there is a need in this industry to provide an improved method of using the e-fuse device that is capable of overcoming the aforesaid problem, thereby increasing the process window, reliability, and thus improving repair yield.